EDN

Exploring new design flows — physical layout

Editor's Note: In Part 3 of this series, consultant and ASIC designer Tom Moxon covered several RTL and logic synthesis design flows. In this installment of the series, he'll describe new physical ...
EDN

Physical Design Flow Taps Partition Layout

Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its usage on a 3 million-gate chip.
Semiconductor Engineering

Secure Physical Design Roadmap Enabling End-To-End Trustworthy IC Design Flow

The FICS Research Institute (University of Florida) has published a new research paper titled “Secure Physical Design.” This is the first and most comprehensive research work done in this area that ...
Semiconductor Engineering

Hyperconvergence Of Design For Test And Physical Design

In today’s highly competitive semiconductor industry, chip-design companies strive for competitive advantages by optimizing designs for PPA (Power, Performance, Area). Along with the functional logic, ...
Electronic Design

Physical Verification Tool Runs From Inside Layout Packages

Enabling designers to perform block and cell physical verification from within layout environments such as Cadence's Virtuoso is Mentor Graphics' Calibre Interactive. This latest version in a ...
Electronic Design

Synthesis of Design Rules and Patterns

This file type includes high-resolution graphics and schematics when applicable. Michael White, Director of Product Marketing, Calibre Physical Verification products, Mentor Graphics In recent years, ...